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ASAHI KASEI
[AK2307/LV]
AK2307/LV
SPEECH CODEC for Digital Key telephone (5.0V/3.3V)
GENERAL DISCREPTION AK2307/LV is an integrated LSI with PCM CODEC, Voice path control, MIC amplifier and Handset driver suitable for PBX/KTS digital key telephone, VoIP Telephone. PCM CODEC is compliant to ITU specification, very low noise, and low power dissipation CODEC. A-law and u-law selectable through Serial I/F register. PCM I/F provides Long/Short frame format and GCI. The output is 8bit compressed data along with 16bit linear format. Voice path block consists of Tone generator, Volume for both TX and RX, Analog inputs, outputs for Handset speaker and the speaker for hands-free conversation, and the path control switch. Side tone can be added internally and its volume is controlled through serial I/F. FEATURES 2 MIC AMP for the handset and microphone are integrated. A 150 ohm handset driver and an extra 150 ohm driver for a headset receiver are provided. Path control and volume control via serial CPU I/F programmable tone generator 5.0V+/-5%, 3.3V+/-0.3V single power supply Low noise, low power consumption Package 28pin VSOP package - Package size; 9.8*7.6mm(pin to pin) - Pin pitch; 0.65mm
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BLOCK DIAGRAM
[AK2307/LV]
Handset Mic I/F HANDT4
HANDT1 HANDT2 HANDT3
upto +25dB VOL1 +14dB SW1 Amp1 +14dB SW2 SW3 +0dB Amp3
TX Digital Attenuator
16 steps by 1dB +7 to -8dB
AGC A/D
(Back ground Noise ATT)
8 steps by 3dB 0 to -21dB
Linear A/u
External Mic I/F MIC3
MIC1 MIC2 Amp2
16 Steps Side Tone by 3dB Digital ATT -12 to -57dB
PCM Interface
16bit Linear or A/u-law DX DR FS BCLK
PCM CODEC
RX Digital Volume
DAOUT
D/A
RAIN
VOL2 24 steps by 1dB 0 to -23dB
0dB/+3dB SW4 SW5
VOL3 24 steps by 1dB 0 to -23dB
+
PAD 0/-9dB
8 steps by 3dB +6 to -21dB
Linear A/u
Handset Receiver output
HANDR
-1 150ohm Driver
VOL4 16 steps by 3dB 0 to -45dB
-1 SW10 150ohm Driver
Tone Gen H (DTMF-H)
PLL Clock generator
PLLCAP
Headset Receiver output
HEADO
0dB/+3dB Amp5
+
L_ATT -2.5dB Tone Gen L (DMTF-L) CPU Interface
CSN SCLK DATA
SW6 SW7
0dB/+3dB
VOL5 16 steps by 2dB 0 to -30dB
SW8 SW9
VREF
Voltage Reference
TAGND
Speaker output
SPO
Amp10
RAGND 10K ohm Driver AVDD AVSS DVDD DVSS EXRIN
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PIN ASSIGNMENT
[AK2307/LV]
HANDR HEADO VSS VDD FS DX BCLK DR DATA SCLK CSN AVDD MIC2 MIC1
1 2 TOP VIEW 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PLLCAP SPO EXRIN RAIN DAOUT RAGND VREF AVSS TAGND HANDT3 HANDT2 HANDT1 HANDT4 MIC3
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PIN CONDITIONS
[AK2307/LV]
Pin types; NIN: Normal Input NOUT: Normal Output TOUT: Tri-state output AOUT: Analog output PWR: Power supply AIN: Analog Input Table 1 Name HANDT2 HANDT3 HANDT1 HANDT4 HANDR MIC3 MIC2 MIC1 DAOUT RAIN HEADO SPO EXRIN DATA SCLK CSN DR DX BCLK FS DVSS DVDD AVSS AVDD PLLCAP TAGND RAGND VREF Type AIN AIN AOUT AIN AOUT AIN AIN AOUT AOUT AIN AOUT AOUT AIN I/O Pin function Max MIn Cap load Res load comment
Analog input for Handset microphone Analog input for Handset microphone OPamp output for Handset microphone Analog input for A/D converter Analog output for Handset receiver 1000pF 150ohm nd 2 Analog input for A/D converter Analog input for External microphone Output of External microphone amplifier Analog output of D/A converter Analog input to RX voice path RX output for Headset receiver 1000pF 150ohm RX output for External Speaker Driver 20pF 10kohm External input for Speaker pre-driver Data input for internal register access 50pF Serial data clock for internal register NIN access NIN Chip select input NIN RX PCM data serial input TOUT TX PCM data serial output. Tri-state output 50pF NIN Bit clock input for DR, DX NIN 8KHz frame sync signal input for PCM I/F PWR Power supply for digital block:0V PWR Power supply for digital block: 3.3V PWR Power supply for Analog block:0V PWR Power supply for Analog block: 3.3V Output to connect the PLL loop filter 1.0uF external AOUT Capacitance capacitance 1.0uF external AOUT TX side Analog ground output. capacitance 1.0uF external AOUT RX side Analog ground output capacitance 1.0uF external AOUT Voltage reference output capacitance
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ASAHI KASEI ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Power Supply Voltages Analog/Digital Power Supply VDD -0.3 6.5 VSS Voltage VSS -0.1 0.1 Digital Input Voltage VTD -0.3 VDD+0.3 Analog Input Voltage VTA -0.3 VDD+0.3 Input current (except power supply pins) IIN -10 10 Storage Temperature Tstg -55 125 Warning: Exceeding absolute maximum ratings may cause permanent damage. Normal operation is not guaranteed at these extremes.
[AK2307/LV]
Units V V V V mA o C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Power Supplies Analog/Digital power supply( AK2307LV) VDD Analog/Digital power supply( AK2307) VDD Ambient Operating Temperature Ta Frame Sync Frequency FS Note) All voltages reference to ground : VSS=0V Min 3.0 4.75 -10 Typ 3.3 5.0 8 Max 3.6 5.25 85 Units V V o C kHz
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FUNCTIONAL DISCRIPTIONS
[AK2307/LV]
1. SERIAL INTERFACE
The internal registers can be read/written via serial CPU interface which consists of SCLK, DATA, and CSN pin. 1 word consists of 16bits. The first 3bits are the instruction code which specifies read or write. The following 4bits specify the address. The rest of 8bits are the data stored in the internal registers. Table1-A CPU I/F ADDRESS/DATA STRUCTURE B15 B14 B13 B12 B11 B10 B9 B8 I2 I1 I0 A3 A2 A1 A0 * *
B7 D7
B6 D6
B5 D5
B4 D4
B3 D3
B2 D2
B1 D1
B0 D0
Instruction code (3 bit )
Address (4bit)
Data for internal registers (8bit)
*)Dummy bit for adjusting the I/O timing when reading register.
Table1-B INSTRUCTION CODE
I2 1 1
I1 1 1 Others
I0 0 1
Read/Write Read Write No action
1-2
Timing of the Serial Interface
SCLK and DATA timing in WRITE/READ operation
(1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CSN. (3) When CSN is "L" and more than 16 SCLK pulses: th [WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16 pulse. th [READ] DATA pin becomes an input pin at the falling edge of the SCLK 16 pulse.
CSN timing and WRITE/READ CANCELLATION
(1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse. th (2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse.
th
SERIAL WRITE/READ ACCESS timing (SERIAL ACCESS MODE)
(1) Serial write and read operation will be done by feeding the another 16 SCLK pulse and st data after 1 write or read operation. st nd (2) It is not necessary to make CSN high between 1 operation and 2 operation.
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WRITE Continuous SCLK
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
[AK2307/LV]
Goes up anytime after SCLK 16th pulse and before 32nd pulse
1
2
3
4
8
9
15
16
1
1
1
0
0
0
0
*
D7
D0
Z
1
1
1
D7
D1
D0
Z
Instruction Code
Address "0000"
Write data to address"000"
WRITE at the rising edge of SCLK 16th pulse
Instruction Code
Write data
Burst SCLK SCLK can be stoped at "H" level or "L" level at anytime during the write cycle. After resuming the SCLK, write cycle is retrieved normally.
Goes up anytime after SCLK 16th pulse and 32nd pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
1
1
0
0
0
0
*
D7
D0
Z
Instruction Code
Address "0000"
Write data to address "000"
WRITE at the rising edge of SCLK 16th pulse
CANCELLATION
CSN goes "H" before the rising edge of 16th SCLK pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
1
1
0
0
0
0
*
D7
D0
Z
Instruction Code
Address "0000"
Write data to address"000"
Write is not Excuted
Z
DATA pin: Input mode (Hi-Z)
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SERIAL ACCESS Serial access can be done by CSN staying "L" during the serise of write cycle.
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16 1 2 3 4 8 9
[AK2307/LV]
15
16
1
1
1
0
0
0
0
*
D7
D0
Z
1
1
1
1
D7
D1 D0 Write data
Z
Instruction Code
Address "0000"
Write data to Address"000" EXCUTE!
Instruction Code
EXCUTED!
READ Continuous SCLK
Can be going up at anytime after SCLK 16th pulse and before 32nd pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
2
3
4
8
9
15
16
1
1
0
A3 A2
A1 A0
Z
D7
D0
Z
1
1
1
0
D7
D1 D0
Z
Read Instruction
Address
Read Data
Read Instruction
Read Data
Data output starts at the falling edge of SCLK 8th pulse
Read period until the earlier edge of either CSN rising or SCLK 16th pulse falling
Burst SCLK
Can be going up at anytime after SCLK 16th pulse and before 32nd pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
1
0
A3 A2
A1 A0
Z
D7 Read Data
D0
Z
Read Instruction
Address
Read output starts at the falling edge of SCLK 8th pulse
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SERIAL ACCESS Serial access can be done by CSN staying "L" during the serise of read cycle
[AK2307/LV]
CSN
SCLK DATA
Z
1
2
3
4
5
6
7
8
9
16
1
2
3
4
8
9
15
16
1
1
0
0
0
0
0
Z
D7
D0
Z
1
1
1
0
Z
Read Instruction
Address "0000"
Read data READ EXCUTED!
Read Instruction READ EXCUTED!
DISCORD OF INSTRUCTION CODE
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
I2
I1
I0
IA3
A2
A1 A0 Address
Z
IInstructions except specified 0bb 10b (b=0 or 1)
WRITE/READ NOT EXCUTED!
Z
DATA pin: Input mode (Hi-Z)
Register Map Register Type : Read/ Write
Add (Hex) 0 1 Register Name (Functions) SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 Path Control 1 RX_ RX Pad Side PCM_1 PCM_0 u/A-law SW10 SW9 Path Control 2 & A_gain -9dB Tone PCM Control 2 0 TX Attenuator VOL1 TX Digital Volume Control 3 RX Volume Side Tone Attenuator RX Digital Volume Control 4 0 0 0 0 VOL4 Tone Volume Control 5 0 0 Tone Freq. Select Tone Generator 1 6 0 L-ATT Tone Freq. Select Tone Generator 2 7 0 0 0 VOL2 RX Handset Volume Control 8 0 0 0 VOL3 RX Headset Volume Control 9 VOL5 RX Speaker Volume Control A AGC_ON Falling time Rising time Threshold level AGC Control B-F Reserved for test use Address "1" ; PCM_1/2 ---- Selection of the PCM interface Mode(Long/Short frame, AK130-1,AK130-2, 16bit linear) Address "6" ; L-ATT ---- -6dB attenuation for Tone generator-L output in case of DTMF tone generation. D7 D6 D5 D4 D3 D2 D1 D0
Bits in which "0" is filled are for test mode activation. Please fill the data "0" for the normal operation. Bits in which "-" is filled are for test use and can not write the data from CPU interface. In case the read operation, data "0" are read from CPU interface.
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ASAHI KASEI 2. PCM Data Interface
[AK2307/LV]
AK2307/LV supports 4 PCM data interface modes. - A/u-Law PCM data mode( Long or Short frame) This mode is for interface of 64kbps PCM data which are compressed /extended by A -law or u-law. Both Long frame and short frame format data are acceptable. The PCM data occupies the first time slot of the PCM data bus which is specified by the frame sync signal. Please refer to the format diagram. - 16 bit Linear data Mode This mode interfaces the 16 bit linear PCM data. PCM CODEC of AK2307/LV operates at 14 bit accuracy. The 2 bits of the LSB are fixed in the 16 bit data stream. - AK130 B1 Mode This mode provides the PCM data Interface to AK130, the TCM transceiver for PBX/KTS system. PCM da ta format is 64kbps A-law or u-law data. The timing between data and FS is different from the A/u -Law PCM data mode written above. In this mode the PCM data are transmitted/received via B1 channel , one of the PCM data channel of the AK130. - AK130 B2 Mode This mode provides the PCM data interface to AK130 B2 channel in as same manner as AK130 B1 Mode. In every modes, the digital voice data are in and out from DR and DX pin and the bit clock and the 8KHz frame sync signal will be fed via BCLK and FS, respectively. The order of PCM and linear data is MSB first . Table 2-A Summary of PCM interface modes
Mode
A/u-Law PCM data mode 16bit Linear data mode AK130 B1 mode AK130 B2 mode
PCM data format
A/u-Law 16bit Linear A/u-Law A/u-Law
BCLK rate
64K x N (N: 1 to 32) 128K x N (N: 1 to 16) 2.048MHz 2.048MHz
frame signal
LF/SF auto select SF only AK130 FS signal AK130 FS signal
st
Time slot
1 Time slot first 16 bit after FS signal xxth time slot of 2.048MHz(B1 channel) xxth time slot of 2.048MHz(B2 channel)
2-1. Selection of the interface mode
These four interface modes are selectable through the CPU register which specified below. A/u-Law selection is also selectable from the same CPU register and it is effective in the u/ A-law interface mode and AK130 B1/B2 modes.
Register Name; Path Control 2 ADD D7 D6 RX 1 Pad
Register Type : Read Write D5 D4 D3 D2
Side Tone PCM_1 PCM_0 u/A law
D1
SW10
D0
SW9
Default
0
0
0
0
0
0
0
0
PCM_10 PCM interface mode select
PCM_1 0 0 1 1 PCM_0 0 1 0 1 Mode A/u-Law PCM data mode 16bit Linear interface mode AK130 B1 mode AK130 B2 mode
u/A-law ; PCM compress/Extend format select A/u-law Compress/Extend 0 u-law
1
A-law
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2-2 Timing and format of the PCM interface
2-2-1 u/A-Law PCM data Mode
[AK2307/LV]
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal. Although there are 32 time slots at maximum in 8kHz frame(when BCK=2.048MHz), PCM data for AK2307/LV occupies first time slot as is indicated in figures below. 2-2-1-a Signals - Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal clock of the LSI is generated based on this FS signal. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 64kHz to 2.048MHz by 64kHz step. - PCM data output (DX) DX is an output signal of 64Kbps PCM u/A -law data. The data is synchronized to the BCLK which determines th e data rate. The period which the PCM data is not occupied, the DX pin turns to Hi -impedance output. In the long frame mode, th the LSB bit turns to Hi-impedance at the faster edge of ether FS falling edge or 9 rising edge of BCLK. - PCM data input (DR) DR is an input signal of 64Kbps PCM u/A -law data. The data is clocked by BCLK at the falling edge and fed into the D/A block. 2-2-1-b LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic selection AK2307/LV monitors the duration of the "H" level of FS and automatically selects LF or SF interface format.
period of FS="H" more than 2 clocks of BCK 1 clock of BCK
2-2-1-c Frame format of the interface Long Frame format
Interface format LF SF
1 2 5 u s (8 K H z )
FS BCLK DX DR
D o n 't c a re
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
D o n 't c a r e
Short Frame format
1 2 5 u s (8 K H z )
FS BCLK DX DR
D o n 't c a re
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
D o n 't c a re
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2-2-2 16 bit Linear PCM data mode
[AK2307/LV]
In this mode the 16 bit linear PCM data are interfaced to the outside. This mode is useful to compress/extend the PCM data by much higher compress rate algorithm than u/A -law algorithm by the external DSP. The AK2307/LV CODEC operates at 14bit accuracy, thus the least 2 bits are output as fixed value. 2-2-2-a Signals - Frame Sync signal (FS) 8kHz reference signal which is same as in u/A -law PCM data mode. How the FS pulse H level width should be 1 clo ck period which is like the short frame FS signal. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 128kHz to 2.048MHz by 128kHz step which is different from in the u/A-law PCM data mode. - PCM data output (DX) DX is an output signal of 128Kbps linear PCM data. The data is synchronized to the BCLK which determines the data rate. The period which the PCM data is not occupied, the DX pin turns to Hi -impedance output. - PCM data input (DR) DR is an input signal of 128Kbps linear PCM data. The data is clocked by BCLK at the falling edge and fed into the D/A block.
16bti Linear Frame format
125us (8KHz)
FS BCLK DX DR Hi-Z * MSB First 1 2 MSB First 1 2 3 3 12 12 13 13 14 14 * * Hi-Z * Hi-Z * 1 1
2-2-3 AK130 B1/B2 Mode
These modes are for connecting the PCM interface to AK130, AKM 's TCM( ping-pong ) transceiver for PBX/KTS system. The PCM data format is A-law or u-law which can be selected by the register. The AK130 B1 mode interfaces the data to B1 channel which is one of two B channels which AK130 provides, and the AK130 B2 mode interfaces to B2 chann el. 2-2-3-a Signals - Frame Sync signal (FS) ___ Please feed the FS signal which is generated by AK130.( F0o , pin#3 ) - Bit Clock (BCLK) BCLK defines the PCM data rate. Please use 2.048MHz clock which is generated by AK130 .( E2o,pin#5 ) - PCM data output (DX) DX is an output signal of 128Kbps linear PCM data. Please connect to the PCM data input pin of AK130.( DSTi,pin#11 ) - PCM data input (DR) DR is an input signal of 128Kbps linear PCM data. The data is clocked by BCLK at the falling edge and fed into the D/A block. Please connect to the PCM data output pin of AK130.( DSTo,pin#6 )
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AK130 B1 Mode
244ns 125us(8kHz) FS BCLK
16CLK
[AK2307/LV]
8CLK MSB First
7 6 MSB First 6
DX DR
* *
Hi-Z
* * * *
2
1
0
Hi-Z
0 * * * *
7
1
Note)*Don't care
AK130 B2 Mode
244ns 125us(8kHz) FS BCLK
24CLK
8CLK MSB First
7 6 MSB First 6
DX DR
* *
Hi-Z
* * * *
2
1
0
Hi-Z
0 * * * *
7
1
Note)*Don't care
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ASAHI KASEI 3. Path and Gain Controls
3-1. Path control switches;
[AK2307/LV]
Voice path, gain control of both RX and TX side, and the tone control are controlled from the CPU registers.
AK2307/LV has 10 analog switches to control the RX and TX analog path. These switches are controlled from following 2 registers, Path control 1/2. Path Control 1 Register Type : Read Write[Address:0000 D7-D0:(SW8-SW1)] ADD D7 D6 D5 D4 D3 D2 0 SW8 SW7 SW6 SW5 SW4 SW3 Default 0 0 0 0 0 0
D1 SW2 0
D0 SW1 0
Path Control 2 Register Type : Read Write[Address:0001 D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)] ADD D7 D6 D5 D4 D3 D2 D1 D0 1 RX RX Side PCM_1 PCM_0 u-law SW10 SW9 _Apad _Pad Tone A-law Default 0 1 0 0 0 0 0 0
Table3-a Switch function
SW Name SW10 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 Function External voice input enable for Speaker RX Tone output enable for Speaker RX Voice path enable for Speaker RX Tone output enable for Headset RX Voice path enable for Headset RX Tone output enable for Handset RX Voice path enable for Handset TX Tone output enable TX MIC path enable TX Handset path enable Polarity 1: External input path 0: Internal Voice path 1: Tone output ON 0: Tone output OFF 1: Voice path ON 0: Voice path OFF 1: Tone output ON 0: Tone output OFF 1: Voice path ON 0: Voice path OFF 1: Tone output ON 0: Tone output OFF 1: Voice path ON 0: Voice path OFF 1: Tone output ON 0: Tone output OFF 1: MIC input ON 0: MIC input OFF 1: Handset path ON 0: Handset path OFF
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3-2 Voice path gain Controls
[AK2307/LV]
AK2307/LV provides the RX and TX voice gain control functions both in analog domain and in digital domain. These gain can be controlled from following five registers.
3-2-1. RX voice path gain controls RX side voice path has three gain control blocks and two gain Pads. These gain stages are controlled through following four registers, Path Control 2, RX digital Volume control, RX handset control, RX Headset control and RX speaker control. Path Control 2 Register Type : Read Write[Address:0001 D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)] ADD D7 D6 D5 D4 D3 D2 D1 D0 1 RX RX Side PCM_1 PCM_0 u-law SW10 SW9 _Apad _Pad Tone A-law Default 0 1 0 0 0 0 0 0
RX_Apad ; Analog +3dB gain pad at three RX voice output amps. This gain for to get the extra gain in the RX level diagram. This means, for example, the analog output will be equivalent to one correspond to -7dBm0 digital code when this gain is enabled. However, please notice the maximum analog output can not exceed the one which is defined in analog characteristics specification. The three gain stages at each output can not be changed individually. Name Porarity Comment RX_Apad 0 1 0dB +3dB
default
RX_Pad; A digital -9dB gain pad at D/A digital domain. This gain pad is for a gain adjustment between the in-system call and the external call. Name Porarity Comment RX_Pad 0 1 0dB -9dB
default
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RX Digital Volume Control Register Type : Read Write[Address:0011 D7-D0(VTX3-VTX0, VSD_3-VSD_0)] ADD D7 D6 D5 D4 D3 D2 D1 D0 3 VRX3 VRX2 VRX1 VRX0 VSD_3 VSD_2 VSD_1 VSD_0 Default 0 1 1 1 1 1 1 1 VRX[3-0]; RX side digital volume from +6dB to -21dB by 3dB step. when VRX3=1 Gain[dB] 3 x VRX[2-0] (VRX[2-0]=1 or 2) VRX3=0 Gain[dB] - 3xVRX[2-0]
VRX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VRX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VRX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VRX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RX digital Attenuator 0dB -3dB -6dB -9dB -12dB -15dB -18dB -21dB NA +3dB +6dB NA NA NA NA NA
[AK2307/LV]
Comment Ref level=0dBm0
default
NA ; Not applicable
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RX Handset Volume Control ( Vol 2 ) Register Type : Read Write [Address:0111 D4-D0(V2_4-V2_0)] ADD D7 D6 D5 D4 D3 D2 7 V2_4 V2_3 V2_2 default 0 0 0 1 1 1 D1 V2_1 1 D0 V2_0 1
[AK2307/LV]
V2_[4-0]; Analog volume for the RX side Handset output. The gain is variable from 0dB to -23dB by 1 dB step. Gain[ dB ] = -V2[dB] (when 0 V2_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
VOL2 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB 18dB -19dB -20dB -21dB -22dB -23dB NA
Comment ref level=0dBm0
default NA ; Not applicable
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RX Headset Volume Control ( Vol 3 ) Register Type : Read Write [Address:1000 D4-D0(V3_4-V2_0)] ADD D7 D6 D5 D4 D3 D2 8 V3_4 V3_3 V3_2 default 0 0 0 1 1 1 D1 V3_1 1 D0 V3_0 1
[AK2307/LV]
V3_[4-0]; Analog volume for the RX side Headset output. The gain is variable from 0dB to -23dB by 1 dB step. Gain[ dB ] = -V3[dB] (when 0 V3_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
VOL3 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB 18dB -19dB -20dB -21dB -22dB -23dB NA
Comment ref level=0dBm0
default
NA ; Not applicable
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RX Speaker Volume Control ( Vol 5 ) Register Type : Read Write [Address:1001 D4-D0(V5_4-V5_0)] ADD D7 D6 D5 D4 D3 D2 9 V5_3 V5_2 default 0 0 0 0 1 1 D1 V5_1 1 D0 V5_0 1
[AK2307/LV]
V5_[4-0]; Analog volume for the RX side Speaker output. The gain is variable from 0dB to -30dB by 2 dB step. Gain[ dB ] = -2 x V5[dB] (when 0 VOL5 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB
Comment ref level=0dBm0
default
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3-2-2. TX voice path gain controls
[AK2307/LV]
TX side voice path has two gain control blocks. One is a analog volume and the other is a digital attenuator after D/A converter. These voice path gains are controlled through the following regi ster.
TX Voice Path Gain Control (TX digital Attenuator, VOL 1) Register Type : Read Write[Address:0010 D6-D0: (VTX2-VTX0, V1_3-V1_0)] ADD D7 D6 D5 D4 D3 D2 D1 2 VTX2 VTX1 VTX0 V1_3 V1_2 V1_1 default 0 1 1 1 0 0 0
D0 V1_0 0
VTX[2-0]; The digital attenuator for TX side voice path. The gain variation is from 0dB to -21dB by 3dB step. Gain[dB] - 3 x VTX( 3dB step )
VTX2 0 0 0 0 1 1 1 1 VTX1 0 0 1 1 0 0 1 1 VTX0 0 1 0 1 0 1 0 1 TX voice path digital Attenuator 0dB -3dB -6dB -9dB -12dB -15dB -18dB -21dB default Comment ref level=0dBm0
V1_[3-0]; An analog volume for TX side voice path. The variable range is from -8dB to +7dB by 1 dB. Gain[dB] ; -8 + V1 ( 1dB step )
V1_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 V1_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 V1_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 V1_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOL1 TX voice path analog volume -8dB -7dB -6dB -5dB -4dB -3dB -2dB -1dB 0dB +1dB +2dB +3dB +4dB +5dB +6dB +7dB ref level=0dBm0 Comment default
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[AK2307/LV]
3-2-3. Side Tone path gain controls AK2307/LV provides the side tone pass from TX to RX in digital domain. The activation of this pass is set through Path Control 1 register( address=0) and the side tone attenuation is controled
through "RX Digital volume control" register( address=2).
Path Control 2 Register Type : Read Write[Address:0001 D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)] ADD D7 D6 D5 D4 D3 D2 D1 D0 1 RX RX Side PCM_1 PCM_0 u-law SW10 SW9 _Apad _Pad Tone A-law Default 0 1 0 0 0 0 0 0
Side Tone; A pass enable of the side tone from TX to RX. Name Porarity Side Tone 0 1 OFF ON
Comment
default
Side Tone digital attenuator gain Register Type : Read Write[Address;0011 D7-D0:(VTX3-VTX0, VSD_3-VSD_0)] ADD D7 D6 D5 D4 D3 D2 D1 D0 3 VRX3 VRX2 VRX1 VRX0 VSD_3 VSD_2 VSD_1 VSD_0 default 0 1 1 1 1 1 1 1 VSD_[3-0]; Side tone digital Attenuator. The gain variation range is from -12dB to -57dB. Gain[dB] -12 -3xVSD
VSD_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VSD_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VSD_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VSD_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Side Tone digital Attenuator gain -12dB -15dB -18dB -21dB -24dB -27dB -30dB -33dB -36dB -39dB -42dB -45dB -48dB -51dB -54dB -57dB default Comment
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ASAHI KASEI 4. Tone generator
[AK2307/LV]
AK2307/LV has two tone generators to generate the service tone, DTMF tone and melody tone. Each generator can select the 42 tone frequencies individ ually, and they are added each other before output from RX receiver amp or TX A/D path. After the adding stage there is a gain stage to attenuate the tone level from 0dB to -45dB by 3dB step. For the DTMF low frequency tone, there is another attenuator to attenuate by -2.5dB which can be set from the register. The signal format is 64 stepwise pseudo sine wave. When the tone frequency is changed, the frequency is changed at the 0 cross point of the tone to prevent the switching noise.
4-1. Tone frequency select
The 43 tone frequencies for the generator -H and the generator-L can be selected individually from the different registers, "Tone generator H-frequency select" and "Tone generator L-frequency select". There is two kind of parameters to select the tone frequency. One is to select the fundamental frequency and another is to select the dividing ratio of the fundamental frequency to get the final tone frequency. For example, when 1600Hz is selected as a fundamental frequency and the number 1/4 is selec ted as a dividing factor, then the final tone frequency shall be 400Hz. Tone generator H-frequency select Register Type : Read Write[Address=0101:
D5-D0:(DIVH_1-DIVH_0, TH_3-TH_0)]
ADD 5 default
D7 0
D6 0
D5 DIVH_1 0
D4 DIVH_0 0
D3 TH_3 0
D2 TH_2 0
D1 TH_1 0
D0 TH_0 0
Tone generator L-frequency select Register Type : Read Write[Address=0110
D6-D0: (LT_ATT, DIVL_1-DIVL_0, TL_3-TL_0)]
ADD 6 default
D7 0
D6 LT_ATT 0
D5 DIVL_1 0
D4 DIVL_0 0
D3 TL_3 0
D2 TL_2 0
D1 TL_1 0
D0 TL_0 0
TH_[3-0] / TL_[3-0]; The select bits of the fundamental frequency for the tone generator -H and the tone generator-L, respectively.
Fundamental frequencies Tx_3 Tx_2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 Tx TH or TL Tx_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Tx_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Fundamental frequency( Hz ) mute 1600.00 1471.26 1391.30 1333.33 1207.55 1174.31 1049.18 1000.00 941.18 888.89 853.33 785.28 771.08 727.27 571.43
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ASAHI KASEI
Tone frequency = fundamental frequency x dividing factor.
[AK2307/LV]
DIVH_[1-0] / DIVL_[1-0]; The dividing factor of the fundamental frequency to get the final tone frequency.
Dividing factor DIVx_1 0 0 1 1 DIVx_0 0 1 0 1 dividing factor 1 1/2 1/4 NA
DIVx ; DIVH or DIVL
Tone frequency list;
Fundamental Freq. (TH,TL3-0) Code 0 1 2 3 4 5 6 7 8 9 A B C D E F Fundamental Freq(Hz) Mute 1600.00 1471.26 1391.30 1333.33 1207.55 1174.31 1049.18 1000.00 941.18 888.89 853.33 785.28 771.08 727.27 571.43 1(Hz) 1600.00 1471.26 1391.30 1333.33 1207.55 1174.31 1049.18 1000.00 941.18 888.98 853.33 785.28 771.08 727.27 571.43
Dividing factor(DIVH/L1-0) 1/2(Hz) 800.00 735.63 695.65 666.67 603.78 587.16 524.59 500.00 470.59 444.49 426.67 392.64 385.54 363.64 285.72 1/4(Hz) 400.00 367.82 347.83 333.33 301.89 293.58 262.30 250.00 235.30 222.25 213.33 196.32 192.77 181.82 142.86
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ASAHI KASEI
functional category of the tone Category Nominal freq. Fundamental Hz Freq(Hz) Melody 1397 1391.3 1318 1333.33 1175 1174.31 1046 1049.18 988 1000 880 882.76 784 785.28 698 1391.3 659 1333.33 587 1174.31 523 1049.18 494 1000 440 882.76 392 785.28 DTMF 697 1391.3 770 771.08 852 853.33 941 941.18 1209 1207.55 1336 1333.33 1477 1471.26 Misc. 726 727.27 4k/n 4k/16=250 1000 4k/12=333.33 1333.33 4k/11=363.64 727.27 4k/10=400 1600 4k/9 =444.44 888.89 4k/8 =500 1000 4k/7 =571.43 571.43 4k/6 =666.67 1333.33 4k/5 =800 1600 4k/4 =1000 1000 Misc. 350 1391.3 440 882.76 600 1174.31 680 1391.3 1600 1600 Dividing Factor 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 4 4 2 4 2 2 1 2 2 1 4 2 2 2 1 Tx_[3-0] Code 0011 0100 0110 0111 1000 1010 1100 0011 0100 0110 0111 1000 1010 1100 0011 1101 1011 1001 0101 0100 0010 1110 1000 0100 1110 0001 1010 1000 1111 0100 0001 1000 0011 1010 0110 0011 0001 DIVx_[1-0] Code 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 10 10 01 10 01 01 00 01 01 00 10 01 01 01 00
[AK2307/LV]
error (Typ) -0.4% +1.1% -0.1% +0.3% +1.2% +0.3% +0.2% -0.3% +1.2% 0.0% +0.3% +1.2% +0.3% +0.2% -0.2% +0.1% +0.2% 0.0% -0.1% -0.2% -0.4% +0.2% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -0.6% +0.3% -2.1% +2.3% 0.0% Comment Fa'' Mi'' Re'' Do'' Si' la' So' Fa' Mi' Re' Do' Si la So Low Low Low Low High High High
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4-2 Tone volume control
[AK2307/LV]
The volume control of the tone is done through "Tone Volume Control" register. The gain is changed after two tones a re added, thus the signal level of two tone is always same. Only L -ATT bit in "Tone generator L-frequency select" register can change the signal level between two tones by -2.5dB. Tone generator L-frequency select Register Type : Read Write[Address=0110
D6-D0: (LT_ATT, DIVL_1-DIVL_0, TL_3-TL_0)]
ADD 6 default
D7 0
D6 LT_ATT 0
D5 DIVL_1 0
D4 DIVL_0 0
D3 TL_3 0
D2 TL_2 0
D1 TL_1 0
D0 TL_0 0
LT_ATT; Attenuation bit for the low frequency tone generator. LT_ATT DTMF Low frequency(Tone generator L) 0 0dB
Comments default
1 -2.5dB *) Gain error of the LT_ATT is +/-1.0dB at the worst case. In this case, LT_ATT is irregular from the DTMF standard. Tone Volume Control (vol 4) Register Type : Read Write[Address=0100:
D3-D0: (V4_3-V4_0)]
ADD 4 default
D7 0
D6 0
D5 0
D4 0
D3 V4_3 1
D2 V4_2 1
D1 V4_1 1
D0 V4_0 1
V4_[3-0]; Tone volume control.( Volume4 ) The gain range is from 0dB to -45dB by 3dB step. Gain[dB] - 3xV4
V4_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
V4_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
V4_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
V4_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VOL4 Tone volume control 0dB -3dB -6dB -9dB -12dB -15dB -18dB -21dB -24dB -27dB -30dB -33dB -36dB -39dB -42dB -45dB
Comment
default
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ASAHI KASEI 5. Power on Reset
[AK2307/LV]
Power on Reset AK2307/LV automatically generates the internal reset pulse which resets all the circuit that is necessary to start the initialization after the power on re set. The CPU registers are set to the default value. After the internal reset pulse is generated, CODEC starts the initialization procedure by being fed FS signal, and it takes 150ms(typ.), 330ms(max) to complete the initialization after the detection of power on. Power up slope to enable the Power-on Reset When the power-up slope is no longer than 50ms(=5tau:tau is time constant), Power On Reset works normally. When the time is longer than 50ms, Power On Reset may not be activated and no internal regist ers are initialized. In this case all registers must be written through CPU interface. NOTE) For the stable operation after power up, we recommend to write all register value through CPU interface in any case after the power up. Recommended start up procedure The following start up procedure is recommended when AK2307/LV is going to power up.
Power up
- FS="L" - BCLK="L"
During this stage, FS and BCLK must be tied to "L" not to receive or transmit the data from/to the external devices.
Wait 200ms
*In case of VDD rising time =50ms(=5tau)
Write data to the internal register through serial I/F
- Write data to the internal register before CODEC starts working.
Supply FS and BCLK
- CODEC Initialization starts. Wait 250ms (min:130ms) - CODEC Initialization complete. CODEC starts working
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ASAHI KASEI ELECTRICAL CHARACTERISTICS
[AK2307/LV]
Unless otherwise noted, guaranteed for VDD=+5.0V+/-5%(AK2307), VDD=+3.3V+/-0.3V(AK2307LV), Ta = o -10 ~ +85 C, FS=8kHz.
DC Characteristics
Parameter Power Consumption BCLK=2048kHz Output High Voltage (CMOS level) Output Low Voltage (CMOS level) Input High Voltage1 (CMOS level) Input Low Voltage1 (CMOS level) Input Leakage Current Input Capacitance Input Leakage Current Output Leakage Current Symbol Conditions Idd * Note1) Min VOH VOL VIH1 VIL1 Ii Ci Ill Ilt -10 -10 -10 IOH=-1.6mA IOL=1.0mA 0.7VDD 0.3VDD +10 5 10 10 VDD-0.5 0.4 Typ 20 Max Units mA V V V V uA pF uA uA
Tri-state mode
*Note1) All the output pin are unloaded. 1020Hz@0dBm0 sine wave from HANDT2/3, A to A loopbacked. All the volume gain are set to 0dB and two of the tone generator are off. The handset mic and receiver paths are only active.
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AC Characteristics
[AK2307/LV]
Note) Otherwise specified, Ta=-10+70 degree, VDD=5.0V +/- 5%(AK2307),VDD=3.3V +/0.3V(AK2307LV), VSS=0V, FS=8kHz are assumed. All the timing parameters are measured at VOH=VDD-0.5, VOL=0.4V. PCM Interface u/A-law modeLong Frame ,Short Frame & Linear PCM mode
Items FS frequency BCLK frequency Note1) Clock width Falling/rising time Output delay Setup time Hold time FS Low level width Pin Name FS BCLK BCLK FS,BCLK,DR DX DX FS DR FS DR FS Parm. FFS FBCLK WP TD TDX TDX2 TFSS TDRS TFSH TDRH TWLFS Conditions Cl=50pF Cl=50pF MIN 160 10 70 40 40 40 1 TYP 8 64xN 128K X N MAX 40 60 Unit kHz kHz ns ns ns ns ns ns ns ns BCLK
Note1Short Frame:64 x N kHz (N=1 to 32), Long Frame:64 x N kHz(N=1 to 32), Linear mode:128 x N kHz(N=1to 16)
AK130 B1ch/B2ch mode
Items FS frequency Clock frequency Pulse width Falling/Rising time Output delay Setup time Hold time Pin Name FS BCLK BCLK FS,BCLK,DR DX DX FS DR FS DR Parm. FFS FBCLK WP TD TDX TDX2 TFSS TDRS TFSH TDRH Conditions CL=50pF CL=50pF MIN TYP 8 MAX Unit kHz kHz ns ns ns ns ns ns ns ns
10 70 40 40 40
2.048 244
-
40 60 60 -
u/A-law PCM modeShort Frame & Linear PCM mode
FFS TFSH TFSS TFSH TFSS
FS
WP WP
BCLK
FBCLK TDX TDX TDX2
DX
TDRS TDRH
DR
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ASAHI KASEI
u/A law PCM modeLong Frame
FFS FWLFS TFSH TFSS TFSH
[AK2307/LV]
FS BCLK
TDX TDX TDX TDX2
DX
TDRS TDRH
DR
AK130 B1ch/B2ch mode
FFS TFSH TFSS TFSH TFSS
FS
WP WP
BCLK
FBCLK TDX TDX TDX2
DX
TDRS TDRH
DR
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CPU I/F
Items SCLK frequency SCLK pulse width Falling/rising time Output delay Setup time Hold time Pin Name SCLK SCLK CSN,SCLK DATA DATA CSN DATA CSN DATA Parm. FSCLK WPS TD TDA TDA2 TCSS TDAS TCSH TDAH Conditions CL=15pF CL=15pF MIN 40 40 40 80 40 TYP MAX 4 100 60 60 -
[AK2307/LV]
Unit MHz ns ns ns Ns ns ns ns ns
Data write cycle
TCSH TCS S TCSH TCS S
CSN
WPS WPS
SCLK
FSCLK TDA S TDAH
DATA
Data read cycle
TCSH TCS S TDA2
CSN
WPS WPS
SCLK
FSCLK TDA S TDAH TD A TD A TD A
DATA
Instruction code, Address write Data read
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CODEC
Absolute Gain (AK2307:VDD=5.0V +/-5%, AK2307LV:VDD=3.3V +/-0.3V ) Parameter Conditions Min Analog Input Level HANDT4 to DX AK2307LV MIC3 to DX AK2307 1020Hz 0dBm0 input Absolute Transmit Gain u/A-law -1.5 Analog Output Level DR to DAOUT AK2307LV 1020Hz 0dBm0 input AK2307 Absolute Receive Gain u/A-law -1.5 Maximum Overload Level DR to DAOUT AK2307LV +3.14dBm0 input AK2307 Gain Tracking Parameter Transmit Gain Tracking Error ( A to D )
[AK2307/LV]
Typ 0.101 0.162 0.482 0.771 0.694 1.107
Max
Units Vrms dB Vrms dB Vrms
+1.5
+1.5
Conditions Reference Level: -51dBm0 ~-46dBm0 -10dBm0 -46dBm0 ~-36dBm0 1020Hz Tone -36dBm0 ~ 0dBm0 Receive Gain Tracking Error Reference Level: -51dBm0 ~-46dBm0 ( D to A ) -10dBm0 -46dBm0 ~-36dBm0 1020Hz Tone -36dBm0 ~ 0dBm0 The characteristics from MIC3 to DR path is guaranteed by the design. Frequency Response Parameter Transmit Frequency Response ( A to D ) HANDT4 to DX MIC3 to DX Receive Frequency Response ( D to A ) DR to DAOUT
Min -0.9 -0.6 -0.4 -0.9 -0.6 -0.4
Typ -
Max 0.9 0.6 0.4 0.9 0.6 0.4
Units dB
dB
Conditions Relative to: 0.06kHz 0dBm0@1020Hz 0.2kHz 0.3 ~3.0kHz 3.4kHz 3.78kHz Relative to: 0.3K ~3.0kHz 0dBm0@1020Hz 3.4kHz 3.78kHz
Min 24 0 -0.3 0 6.5 -0.3 0 6.5
Typ -
Max 2.5 0.3 0.8 0.3 0.8 -
Units
dB
dB
Distortion Parameter Conditions Min Transmit Signal to Distortion 1020Hz Tone -36dBm0 ~-41dBm0 24 ( D to A ) -26dBm0 ~-36dBm0 29 HANDT4 to DX 0dBm0 ~-26dBm0 35 MIC3 to DX Receive Signal to Distortion 1020Hz Tone -36dBm0 ~-41dBm0 24 ( A to D ) -26dBm0 ~-36dBm0 29 DR to DAOUT 0dBm0 ~-26dBm0 35 Note) C-message Weighted for u-Law, Psophometric Weighted for A-Law Note) The characteristics from MIC3 to DR path is guaranteed by the design.
Typ -
Max -
Units dB
dB
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Noise
[AK2307/LV]
Parameter Conditions Min Typ Max Units 1) Idle Channel Noise u-law, C-message 8 16 dBrnC0 A!D HANDT2,3 to DX A-law, Psophometric -82 -74 dBm0p MIC2 to DX 2) Idle Channel Noise u-law, C-message 2 9 dBrnC0 A-law, Psophometric -88 -81 dBm0p D!A DR to DAOUT 2) Idle Channel Noise u-law, C-message 3 16 dBrnC0 A-law, Psophometric -87 -74 dBm0p D!A DR to HANDR1 Note 1) Analog Input = Analog Ground. The gain of Handset MIC and MIC input is assumed as +25dB. SCLK is not supplied. The specification of MIC to DX pass is guaranteed by the design. Note 2) Digital Input(DR) = +0 Code Interchannel Crosstalk Parameter Transmit to Receive HANDT4 to DAOUT MIC3 to DAOUT Receive to Transmit RX voice path Volume Parameter Step margin
Conditions 0dBm0@HANDT4, Idle PCM code@DR
Min -
Typ -70
Max -
Units dB
0dBm0 code@DR, HANDT4 = 0 Vrms
-
-70
-
dB
Volume VOL2 VOL3 VOL5 0 to -22dB VOL5 -22 to -30dB
Conditions 1020Hz 0dBm0 input at DR Relative to: 0dB 1020Hz 0dBm0 input at DR Relative to: 0dB 1020Hz 0dBm0 input at DR Relative to: 0dB 1020Hz 0dBm0 input at DR Relative to: 0dB
Min -1.0 -1.0 -1.0 -1.5
typ 0 0 0 0
max
Unit
+1.0*) dB +1.0*) dB +1.0 dB
+1.5*) dB
*)Monotonus increase/decrease is guaranteed
TX voice path Volume Parameter Step margin Volume VOL1 Conditions 1020Hz 0dBm0 input at DR Relative to: 0dB Min -1.0 typ 0 max Unit
+1.0*) dB
*)Monotonus increase/decrease is guaranteed
Tone Volume Parameter Step margin Volume VOL4 Gain error Conditions Output; HANDR1 1600Hz tone , Ref level;VOL4=0dB L-ATT=-2.5dB 0 to -24dB Min -1.0 typ 0 0 0 max Unit
+1.0 dB +2.0*) dB +1.0 dB
-27 to -45dB -2.0 -1.0
L-ATT
*)Monotonus increase/decrease is guaranteed
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OP-AMPs Note) Otherwise specified, the VOL2 ,3 and 5 is 0dB gain. RX Amp for Handset receiver
[AK2307/LV]
Conditions MIN TYP MAX Unit RAIN AK2307LV (150ohm load) 2.0 Vp-p (75ohm load) 1.5 HANDR1 3.2 SINAD<40d AK2307 (150ohm load) B, 1020Hz (75ohm load) 2.4 Note) when HANDR1 and HEADO are used as a differential output for 150 ohm receiver, the load impedance for the each output is calculated as 75 ohm. Maximum output level RX Amp for Headset receiver Conditions MIN TYP MAX Unit AK2307LV (150ohm load) 2.0 Vp-p (75ohm load) 1.5 AK2307 (150ohm load) 3.2 (75ohm load) 2.4 Note) when HANDR1 and HEADO are used as a differential output for 150 ohm receiver, the load impedance for the each output is calculated as 75 ohm. RX Amp for Speaker output Conditions MIN TYP MAX Unit Maximum output RAIN, EXRIN AK2307LV 2.0 Vp-p level SPO*) SINAD<40dB, AK2307 3.2 1020Hz *NoteA Characteristics from EXRIN input is guaranteed by the design. Maximum output level RAIN HEADO SINAD<40d B, 1020Hz TX Amp for Handset MIC input Maximum output level HANDT1 SINAD<40 dB Mic gain=25dB at 1020Hz Conditions AK2307LV AK2307 Inverting amplify MIN 0.411 0.660 0 TYP MAX 25 dB Unit Vp-p
Maximum gain
TX Amp for MIC input Maximum output level Conditions MIC1 AK2307LV SINAD<40 dB AK2307 Gain=25dB at 1020Hz Inverting amplify MIN 0.411 0.660 0 TYP MAX 25 dB Unit Vp-p
Maximum gain
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Tone signal Output level Output level to RX path Conditions HANDR AK2307LV HEADO SPO AK2307 1600Hz VOL4=0dB DX AK2307/LV 1049Hz VOL4=0dB MIN 420 672 TYP 500 800 0 MAX 595 952
[AK2307/LV]
Unit mVrms
Output level to TX path
dBm0
Input Impedance Pin EXRINRAIN HANDT4MIC3
MIN 70K 7K
TYP 100K 10K
MAX 150K 15K
Unit ohm
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ASAHI KASEI APPLICATION CIRCUIT EXAMPLE
l Handset Input Stage HANDT4
0.1uF 100pF 1.0uF 20K 1.2K
[AK2307/LV]
HANDT1 HANDT2 HANDT3
1.0uF
1.2K
100pF
20K
TAGND
1.0uF
l
MIC amp Input Stage MIC3
0.1uF
100pF
MIC1 MIC2
1.0uF
20K 1.2K
VSS
TAGND l Handset Receiver output Stage Single End Output
0.1uF
DAOUT RAIN Differential Output
0.001uF 10uF
HANDR
HANDR
VSS
-1 HEADO
0.001uF VSS VSS
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ASAHI KASEI
Speaker Amp Output Stage
100pF 100K
[AK2307/LV]
SPO
10K
0.1uF Internal RAGND
l
Analog Ground, PLLCAP VREF
1.0uF
TAGND
1.0uF
RAGND
1.0uF
PLLCAP
1.0uF
l
Power Supplies VDD
10uF 0.1uF
VSS
AVDD
10uF 0.1uF
AVSS
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PACKAGE 28pin VSOP Marking (1) Pin#1 indicator (2) Date code: (3) Marketing code: (4) AKM Logo
[AK2307/LV]
XXXXX5digit AK2307LV/AK2307
AK2307LV
AKM AK2307LV XXXXX
XXXXX: AK2307
Date Code and Lot#
AKM AK2307 XXXXX
XXXXX:
Date Code and Lot#
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Package dimensions
[AK2307/LV]
28pin VSOP (Unit: mm)
*9.80.2
28
15 A 7.60.2 0.15+0.10 -0.05 0.100.05 Detail A 0-10 0.50.2
2005/12 38
1 0.65
0.12
14
0.22+0.10 -0.05 M
Seating Plane 0.08
NOTE: Dimension "*" does not include mold flash.
MS0190-E-05
5.6 1.15 0.10
ASAHI KASEI
[AK2307/LV]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to res ult in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0190-E-05 39 2005/12

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